In the face of so many CPLDs in the market, it is very important for us to choose which one is suitable, so we will solve your problem in the following ways.
Here is the outline:
Feature of different CPLD
CPLD usage
1. EPM7032AETI44-7N
A. High-performance 3.3-V EEPROM-based programmable logic devices (PLDs) built on second-generation Multiple Array MatriX (MAX®) architecture
B. 3.3-V in-system programmability (ISP) through the built-in IEEE Std.
C. Built-in boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1
D. Supports JEDEC Jam Standard Test and Programming Language(STAPL) JESD-71
E. Enhanced ISP features
F. Pin-compatible with the popular 5.0-V MAX 7000S devices
G. High-density PLDs ranging from 600 to 10,000 usable gates
H. Extended temperature range
2. EPM7256SRI208-10N
A. High-performance, EEPROM-based programmable logic devices (PLDs) based on second-generation MAX® architecture
B. Includes 5.0-V MAX 7000 devices and 5.0-V ISP-based MAX 7000S devices
C. Built-in JTAG boundary-scan test (BST) circuitry in MAX7000S devices with 128 or more microcells
D. Complete EPLD family with logic densities ranging from 600 to 5,000 usable gates
E. 5-ns pin-to-pin logic delays with up to 175.4-MHz counter frequencies (including interconnect)
F. PCI-compliant devices available
CPLD is a digital integrated circuit in which users construct logic functions according to their own needs. Here, take the responder as an example to talk about its design (decoration) process, that is, the design process of the chip. Most of the work of CPLD is done on the computer. Open the integrated development software (MAX + pluxii of Altera company) → draw the schematic diagram and write the hardware description language (VHDL, Verilog) → compile → give the input excitation signal of the logic circuit, conduct simulation and check whether the logic output result is correct → conduct pin input Output lock (64 input and output pins of 7128 can be set as needed) → generate code → transmit and store the code in CPLD chip through download cable. The pins of 7128 chip have been led out. The nixie tube, answer switch, indicator light and buzzer need to be connected to the chipboard and can be completed with wires. Power on the test. When the answer switch is pressed, the indicator light of the corresponding position should be on. After the answer is correct, the referee will give extra points to see whether the score result of the digital display is correct. If there are problems, the schematic diagram or hardware description language can be modified again, Perfect the design. After the design is completed, if it is mass-produced, other CPLD chips can be copied directly, that is, the code can be written. If the chip is to be designed in other ways, such as traffic light design, it is necessary to redraw the schematic diagram or write the hardware description language, repeat the above work process and complete the design. This modified design is equivalent to redecorating the house, which can be carried out tens of thousands of times for CPLD.
