EPM9560RC304-15

Product Attributes

Features：

■ High-performance CMOS EEPROM-based programmable logic

devices (PLDs) built on third-generation Multiple Array MatriX (MAX®) architecture

■ 5.0-V in-system programmability (ISP) through built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface

■ Built-in JTAG boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1-1990

■ High-density erasable programmable logic device (EPLD) family ranging from 6,000 to 12,000 usable gates (see Table 1) ■ 10-ns pin-to-pin logic delays with counter frequencies of up to 144 MHz

■ Fully compliant with the peripheral component interconnect Special

Interest Group’s (PCI SIG) PCI Local Bus Specification, Revision 2.2

■ Dual-output macrocell for independent use of combinatorial and registered logic

■ FastTrack® Interconnect for fast, predictable interconnect delays

■ Input/output registers with clear and clock enable on all I/O pins

■ Programmable output slew-rate control to reduce switching noise

■ MultiVolt™ I/O interface operation, allowing devices to interface with 3.3-V and 5.0-V devices

■ Configurable expander product-term distribution allowing up to 32 product terms per macrocell

■ Programmable power-saving mode for more than 50% power reduction in each macrocell

and More Features：

■ Programmable macrocell flipflops with individual clear, preset, clock, and clock enable controls

■ Programmable security bit for protection of proprietary designs

■ Software design support and automatic place-and-route provided by Altera’s MAX+PLUS® II development system on Windows-based

PCs as well as Sun SPARCstation, HP 9000 Series 700/800, and IBM RISC System/6000 workstations

■ Additional design entry and simulation support provided by EDIF 2 0 0 and 3 0 0 netlist files, library of parameterized modules (LPM),

Verilog HDL, VHDL, and other interfaces to popular EDA tools from manufacturers such as Cadence, Exemplar Logic, Mentor Graphics,

OrCAD, Synopsys, Synplicity, and VeriBest

■ Programming support with Altera’s Master Programming Unit (MPU), BitBlasterTM serial download cable, ByteBlasterTM parallel port download cable, and ByteBlasterMVTM parallel port download cable, as well as programming hardware from third-party

manufacturers

■ Offered in a variety of package options with 84 to 356 pins (see Table 2)

The MAX 9000 family is supported by Altera’s MAX+PLUS II development system, a single, integrated software package that offers

schematic, text—including VHDL, Verilog HDL, and the Altera Hardware Description Language (AHDL)—and waveform design entry,

compilation and logic synthesis, simulation and timing analysis, and device programming. The MAX+PLUS II software provides EDIF 2 0 0

and 3 0 0, LPM, and other interfaces for additional design entry and simulation support from other industry-standard PC- and UNIX

workstation-based EDA tools. The MAX+PLUS II software runs on Windows-based PCs as well as Sun SPARCstation, HP 9000 Series

700/800, and IBM RISC System/6000 workstations.

Functional Description：

MAX 9000 devices use a third-generation MAX architecture that yields both high performance and a high degree of utilization for most

applications. The MAX 9000 architecture includes the following elements:

■ Logic array blocks

■ Macrocells

■ Expander product terms (shareable and parallel)

■ FastTrack Interconnect

■ Dedicated inputs

■ I/O cells