IC CONFIG DEVICE 1MBIT 8DIP |
EPC1PI8N
Intel
ICPlanet
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Product Attributes
TYPE | DESCRIPTION |
Category | Integrated Circuits (ICs) |
Memory - Configuration Proms for FPGAs | |
Mfr | Intel |
Series | EPC |
Package | Tube |
Part Status | Obsolete |
Programmable Type | OTP |
Memory Size | 1Mb |
Voltage - Supply | 3V ~ 3.6V, 4.5V ~ 5.5V |
Operating Temperature | ·-40℃ ~+ 85℃ |
Mounting Type | Through Hole |
Package / Case | 8-DIP (0.300", 7.62mm) |
Supplier Device Package | 8-PDIP |
EPC devices offer the following features:
• Single-chip configuration solution for Altera® ACEX® 1K, APEX® 20K (including APEX 20K, APEX 20KC, and APEX 20KE), APEX II, Arria® GX, Cyclone® , Cyclone II, FLEX® 10K (including FLEX 10KE and FLEX 10KA), Mercury®, Stratix® II, and Stratix II GX devices
• Contains 4-, 8-, and 16-Mb flash memories for configuration data storage
• On-chip decompression feature almost doubles the effective configuration density
• Standard flash die and a controller die combined into single stacked chip package
• External flash interface supports parallel programming of flash and external processor access to unused portions of memory
• Flash memory block or sector protection capability using the external flash interface
• Supported in EPC4 and EPC16 devices
• Page mode support for remote and local reconfiguration with up to eight configurations for the entire system
• Compatible with Stratix series remote system configuration feature
• Supports byte-wide configuration mode fast passive parallel (FPP) with an 8-bit data output per DCLK cycle
• Supports true n-bit concurrent configuration (n = 1, 2, 4, and 8) of Altera FPGAs
• Pin selectable 2-ms or 100-ms power-on reset (POR) time
• Configuration clock supports programmable input source and frequency synthesis
• Multiple configuration clock sources supported (internal oscillator and external clock input pin)
• External clock source with frequencies up to 100 MHz
• Internal oscillator defaults to 10 MHz and you can program the internal oscillator for higher frequen‐cies of 33, 50, and 66 MHz
• Clock synthesis supported using user programmable divide counter
• Available in the 100-pin plastic quad flat pack (PQFP) and the 88-pin Ultra FineLine BGA (UFBGA) packages
• Vertical migration between all devices supported in the 100-pin PQFP package
• Supply voltage of 3.3 V (core and I/O)
• Hardware compliant with IEEE Std. 1532 in-system programmability (ISP) specification
• Supports ISP using Jam Standard Test and Programming Language (STAPL)
• Supports JTAG boundary scan
• The nINIT_CONF pin allows private JTAG instruction to start FPGA configuration
• Internal pull-up resistor on the nINIT_CONF pin always enabled
• User programmable weak internal pull-up resistors on nCS and OE pins
• Internal weak pull-up resistors on external flash interface address and control lines, bus hold on data lines
• Standby mode with reduced power consumption
Note: For more information about FPGA configuration schemes and advanced features, refer to the
configuration chapter in the appropriate device handbook.
Product Attributes
TYPE | DESCRIPTION |
Category | Integrated Circuits (ICs) |
Memory - Configuration Proms for FPGAs | |
Mfr | Intel |
Series | EPC |
Package | Tube |
Part Status | Obsolete |
Programmable Type | OTP |
Memory Size | 1Mb |
Voltage - Supply | 3V ~ 3.6V, 4.5V ~ 5.5V |
Operating Temperature | ·-40℃ ~+ 85℃ |
Mounting Type | Through Hole |
Package / Case | 8-DIP (0.300", 7.62mm) |
Supplier Device Package | 8-PDIP |
EPC devices offer the following features:
• Single-chip configuration solution for Altera® ACEX® 1K, APEX® 20K (including APEX 20K, APEX 20KC, and APEX 20KE), APEX II, Arria® GX, Cyclone® , Cyclone II, FLEX® 10K (including FLEX 10KE and FLEX 10KA), Mercury®, Stratix® II, and Stratix II GX devices
• Contains 4-, 8-, and 16-Mb flash memories for configuration data storage
• On-chip decompression feature almost doubles the effective configuration density
• Standard flash die and a controller die combined into single stacked chip package
• External flash interface supports parallel programming of flash and external processor access to unused portions of memory
• Flash memory block or sector protection capability using the external flash interface
• Supported in EPC4 and EPC16 devices
• Page mode support for remote and local reconfiguration with up to eight configurations for the entire system
• Compatible with Stratix series remote system configuration feature
• Supports byte-wide configuration mode fast passive parallel (FPP) with an 8-bit data output per DCLK cycle
• Supports true n-bit concurrent configuration (n = 1, 2, 4, and 8) of Altera FPGAs
• Pin selectable 2-ms or 100-ms power-on reset (POR) time
• Configuration clock supports programmable input source and frequency synthesis
• Multiple configuration clock sources supported (internal oscillator and external clock input pin)
• External clock source with frequencies up to 100 MHz
• Internal oscillator defaults to 10 MHz and you can program the internal oscillator for higher frequen‐cies of 33, 50, and 66 MHz
• Clock synthesis supported using user programmable divide counter
• Available in the 100-pin plastic quad flat pack (PQFP) and the 88-pin Ultra FineLine BGA (UFBGA) packages
• Vertical migration between all devices supported in the 100-pin PQFP package
• Supply voltage of 3.3 V (core and I/O)
• Hardware compliant with IEEE Std. 1532 in-system programmability (ISP) specification
• Supports ISP using Jam Standard Test and Programming Language (STAPL)
• Supports JTAG boundary scan
• The nINIT_CONF pin allows private JTAG instruction to start FPGA configuration
• Internal pull-up resistor on the nINIT_CONF pin always enabled
• User programmable weak internal pull-up resistors on nCS and OE pins
• Internal weak pull-up resistors on external flash interface address and control lines, bus hold on data lines
• Standby mode with reduced power consumption
Note: For more information about FPGA configuration schemes and advanced features, refer to the
configuration chapter in the appropriate device handbook.